JUYI
JUYI 90V Three-Phase Gate Driver Chip JY213L for BLDC Motor Driver Boards
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JUYI 90V Three-Phase Gate Driver Chip JY213L for BLDC Motor Driver Boards
DESCRIPTION
The JY213L is a high-speed 3-phase gate driver for power MOSFET and IGBT devices with three independent
high and low side referenced output channels. Built-in dead time protection and shoot-through protection
prevent damage to the half-bridge. The UVLO circuits prevent malfunction when VCC and VBS are lower
than the specified threshold voltage. A novel high-voltage BCD process and common-mode noise canceling
technique provide stable operation of high-side drivers under high dV/dt noise conditions while achieving
excellent negative transient voltage tolerance. An enable pin (EN) is included so that standby mode may be
used to set the chip into a low quiescent current state to realize long battery lifetime.
FEATURES
• Integrated 90V half-bridge high side driver
• Ability to drive up to 3-phase half-bridge gates
• Built-in boot strap diode for each high side channel
• Built-in dead time protection
• Shoot-through protection
• Under voltage lockout for VCC and VBS
• Low operation voltage 0–5.5V for VCC and VBS
• 3.3V and 5V input logic compatible
• Enable pin (EN) for low standby current
• IO+/IO-: +1.2A/–2.0A atVCC=15V, VBS=15V
• Built-in dead time： 0.5 us (typ.)
• Common-mode dV/dt noise cancellation circuit
• Tolerant of negative transient voltage
• Low dI/dt gate drive for better noise immunity
• –40ºC to 125ºC operating range
• Small footprint package ：TSSOP20L/24L,173mil
APPLICATION
• E-BIKE/electric power tool 3-phase motor driver
• Battery-powered mini/micro motor control
• General purpose inverter
BLOCK DIAGRAM
TYPICAL APPLICATION CIRCUIT
PIN CONFIGURATION
TSSOP20L AND TSSOP24L PACKAGE
PIN DESCRIPTION
FUNCTION DESCRIPTION
LOW SIDE POWER SUPPLY: VCC
VCC is the low side supply and it provides power to both input logic and low side output power stage. The built-in
under-voltage lockout circuit enables the device to operate at sufficient power when a typical VCC supply voltage
higher than VCCUV+ =4.2V is present, shown as FIG. 1. The JY213L shuts down all the gate driver outputs, when
the VCC supply voltage is below VCCUV- =3.8 V, shown as FIG. 1. This prevents the external power devices against
extremely low gate voltage levels during on-state which may result in excessive power dissipation.
FIG. 1 VCC supply UVLO operating area
HIGH SIDE POWER SUPPLY: VBS (VB1-VS1, VB2-VS2, VB3-VS3)
VBS is the high side supply voltage. The total high side circuitry may float with respect to COM following the external
high side power device emitter/source voltage. Due to the internal low power consumption, the entire high side
circuitry may be supplied by bootstrap topology connected to VCC, and it may be powered with small bootstrap
capacitors. The device operating area as a function of the supply voltage is given in FIG.2.
FIG. 2 VBS supply UVLO operating area
LOW SIDE AND HIGH CONTROL INPUT LOGIC: HIN&LIN (HIN1,2,3/LIN1,2,3)
The Schmitt trigger threshold of each input is designed low enough to guarantee LSTTL and CMOS compatibility down
to 3.3V controller outputs. Input Schmitt trigger and advanced noise filtering provide noise rejection of short input pulses.
An internal pull-down resistor of about 100kΩ (positive logic) pre-biases each input during VCC supply start-up state.
The minimum recommended input pulse-width is 300ns for proper operation of the driver.
SHOOT-THROUGH PREVENTION
The JY213L is equipped with shoot-through protection circuitry (also known as cross conduction prevention circuitry).
FIG. 3 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the sametime.
When the inputs controlling both high-side and low-side drivers are both logic IGH, then both driver outputs are pulled
down to logic LOW to shut down two power devices in the same bridge.
FIG. 3 Shoot-through prevention
DEAD TIME PROTECTION
The JY213L features integrated fixed dead time protection circuitry. The dead time feature inserts a time period
(a minimum dead time) in which both the high- and low-side power switches are held off. This is done to ensure
that the power switch has fully turned off before the second power switch is turned on. This minimum dead
time is automatically inserted whenever the external dead time is shorter than DT. External dead times larger
than DT are not modified by the gate driver. FIG. 4 illustrates the dead time period and the relationship
between the output gate signals.
FIG. 4 Dead time protection
GATE DRIVER (HO1,2,3/ LO1,2,3)
Low side and high side driver outputs are specifically designed for pulse operation and dedicated to drive power devices
such as IGBT and power MOSFET. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are only changed at the edge of the respective inputs. After releasing from an under-voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side output.
In contrast, after releasing from an under-voltage condition of the VCC supply, the low side outputs may directly switch
to the state of their respective inputs without the additional constraints of the high side driver.
STANDBY MODE
The JY213L packaged in TSSOP24L provides an enable pin (EN) to allow the device to work in a low current dissipation state.
Pin EN is compatible with 3.3/5V logic level. If EN is set to logic HIGH, the device is forced into standby mode and all gate
driver outputs are locked into a logic LOW state and only 16μA (typ.) is dissipated. If EN goes from logic HIGH to logic LOW
and incorporates a delay of 6μs (typ.), the device may be released from standby mode and all outputs are enabled.
In order to lower the bias current, a sufficiently large resistor (100kΩ) is tied between EN and COM.
ABSOLUTE MAXIMUM RATINGS
Stresses exceeding the absolute maximum ratings may damage the device or cause abnormal function. All the voltage
parameters are absolute voltages referenced to IC COM unless otherwise stated in the table.
Note:
①: PD and RthJA are only guaranteed by design.
RECOMMENDED OPERATING CONDITIONS
②: For VBS=15V, normal logic operation for VS is between COM–6V to 90V. High-side circuitry will sustain current state ifVS is
between COM–6V to COM–VBS. The parameter is only guaranteed by design.
PACKAGE INFORMATION
20 PINS, TSSOP, 173MIL
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